Figure 1: In FPGA co-processing, images are acquired using the CPU and then sent to the FPGA via DMA so the FPGA can perform operations. |
Figure 2: In the inline FPGA processing architecture, the camera interface is connected directly to the pins of the FPGA so the pixels are passed directly to the FPGA as they are sent from the camera. |
Figure 3: Since FPGAs are massively parallel in nature, they can offer significant performance improvements over CPUs. |
Figure 4: Running this vision algorithm using an FPGA co-processing architecture yields 20 times more performance than a CPU-only implementation. |
Figure 5: Developing an algorithm in a configuration-based tool for FPGA targets with integrated benchmarking cuts down on the time spent waiting for code to compile and accelerates development. |